Senior STA Lead - Timing Analysis

Role Overview

The Senior Static Timing Analysis (STA) Lead at Advanced Micro Devices is primarily responsible for timing closure and optimization of cutting-edge CPU/APU designs. This critical engineering role ensures that designs operate effectively at top industry frequencies and involves close collaboration with various engineering teams to achieve seamless integration and performance.

Experience Level

The position requires 10+ years of expertise specifically in Static Timing Analysis within high-performance digital design, alongside 5+ years in CPU or GPU ASIC design.

Key Responsibilities

The responsibilities include leading static timing analysis and managing timing closure processes for high-frequency cores, conducting thorough timing sign-offs, and maintaining timing constraints. The STA Lead will also need to analyze critical paths for both performance and power efficiency, engage in timing ECOs, and collaborate on yield improvements.

Requirements

Candidates must possess strong experience in handling timing limitations and variabilities, particularly in relation to voltage droops and aging effects. Proficiency in statistical analysis methodologies and comprehensive knowledge of physical design strategies are essential. Familiarity with industry-standard tools such as Synopsys and Cadence products, as well as a foundation in machine learning applications related to timing optimization, will be advantageous.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is required to qualify for this role.