Senior STA Engineer, Sub-Chip

Role Summary

The Senior STA Engineer for Sub-Chip at NVIDIA will play a crucial role in performing advanced Static Timing Analysis (STA) at the chiplet and FC level. This includes running Prime Time, reviewing and debugging timing paths, and generating necessary constraints and timing ecosystems. You will also identify convergence risks and collaborate intensively with the physical design, RTL, and DFT teams to ensure project milestones are met.

Experience Level

This position requires at least 5 years of practical experience in Static Timing Analysis (STA), showcasing a strong background in using Prime Time and adhering to signoff methodologies.

Responsibilities

• Execute advanced Static Timing Analysis (STA) on chiplets and FC level.
• Utilize Prime Time to review and debug timing paths.
• Generate and understand constraints, as well as manage SDC generation and timing ecosystems.
• Identify convergence risks while collaborating with physical design and RTL teams throughout project stages.
• Oversee the full timing closing process, ensuring quality approval from pre-layout STA model through signoff.

Requirements

A B.Sc. or M.Sc. in Electrical Engineering is required. Candidates must possess deep hands-on experience in STA and have excellent leadership capabilities.

Education Requirements

Applicants should hold at least a Bachelor’s degree in Electrical Engineering or a related field.