Role Summary
The Senior Software Engineer in the QA department is responsible for ensuring quality aspects and assessment of components under Lattice Radiant tool, specifically focusing on static timing analysis (STA).
Experience Level
Senior level, requiring 5+ years of experience in EDA / RTL development / verification.
Responsibilities
The role includes key responsibilities such as:
- Verifying the accuracy and reliability of the static timing analysis (STA) software in Radiant.
- Creating and maintaining test suites to ensure correct path delay calculations and accurate reporting of setup/hold violations.
- Monitoring regressions, analyzing failures, and reporting them for fixes.
- Preparing and executing test plans for upcoming features/changes in STA.
- Ensuring that delay calculations by STA match hardware expectations.
Requirements
Essential skills include:
- Very strong understanding of FPGA architectures.
- Good understanding of Lattice Diamond/Radiant or similar FPGA tool flow.
- Experience with RTL using Verilog.
- Strong understanding of constraints handling, preferably with SDC.
- Exposure to timing analyser concepts and tools.
- Strong debugging skills.
Additionally, the following skills are beneficial:
- Experience with scripting languages like Python, Perl, TCL.
- Experience with high-speed I/O (PCIe, DDR) and their timing requirements.
Education Requirements
BS/MS in Electrical, Electronics, Computer Science, or Computer Engineering required.
About the Company
Company: Lattice Semiconductor
Headquarters: Portland, Oregon, USA
Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.

Date Posted: 2026-03-24