Senior Soft IP Design Engineer

Role Summary

The Senior Soft IP Design Engineer plays a critical role in developing Connectivity IP portfolios for Lattice's FPGA products. The engineer must have strong technical leadership skills to collaborate with architects in transforming specifications into optimized high-speed RTL designs, ensuring optimal performance, power efficiency, and logic utilization.

Experience Level

Applicants should possess a minimum of 7 years of experience in FPGA IP design, showcasing a robust background in the required technologies.

Responsibilities

• Translating specifications into high-speed RTL designs.
• Ensuring design performance, power effectiveness, and efficient logic utilization.
• Collaborating with architects on design specifications and requirements.
• Leading initiatives in high-speed SERDES and relevant video protocols.
• Engaging in hardware validation and interoperability testing.

Requirements

• Proficiency in high-speed SERDES and video protocols such as DisplayPort, HDMI, MIPI, and SDI.
• Hands-on experience with FPGA RTL design, including CDC/lint verification and timing closure.
• Strong programming skills in languages like Verilog, SystemVerilog, C/C++, Perl, TCL, or Python.
• Experience in soft IP packaging, example design, and testbench development is a plus.

Education Requirements

A Bachelor's, Master's, or PhD in Electronics or Computer Engineering is required to meet the technical demands of this position.