Senior Soft IP Design Engineer

Job Title

Senior Soft IP Design Engineer

Role Summary

Develop and maintain connectivity soft IP for Lattice FPGAs. Translate architecture and specifications into high-speed RTL implementations optimized for performance, power, and logic utilization.

Provide technical leadership within the IP team, collaborating with architects, verification, validation, and system engineers to deliver validated IP cores.

Experience Level

Senior — minimum 7 years of FPGA IP design experience.

Responsibilities

The role is responsible for delivering production-quality soft IP and supporting its integration and validation.

• Translate specifications into synthesizable RTL and ensure design meets performance, power, and area targets.
• Collaborate with architects, verification, and silicon validation teams to define and implement IP features and interfaces.
• Perform CDC analysis, linting, functional debug, and timing closure activities.
• Develop example designs, testbenches, and soft IP packaging for customer and lab use.
• Plan and execute hardware validation and interoperability testing with target platforms.
• Provide technical mentorship and contribute to design reviews and IP roadmaps.

Requirements

Must-have technical skills and experience; nice-to-have items are noted.

• Hands-on FPGA RTL design experience, including CDC handling, linting, verification workflows, debug, and timing closure.
• Proficient in Verilog and SystemVerilog; experience with C/C++, Python, TCL or Perl for tooling and scripts.
• Experience with hardware validation or interoperability testing on target platforms.
• Experience developing soft IP packaging, example designs, and testbenches (preferred).
• Familiarity with high-speed SERDES and video protocols (DisplayPort, HDMI, MIPI, SDI) or peripherals (SPI, I2C, I3C) is a plus.
• Independent, self-motivated, and able to operate effectively in a dynamic engineering environment.
• Must be able to provide proof of right to work in Malaysia and pass background/reference checks.

Education Requirements

BS, MS, or PhD in Electronics, Electrical or Computer Engineering (or equivalent practical experience). Minimum 7 years of FPGA IP design experience is expected.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.