Senior SoC Logic Design Engineer

Role Summary

As a Senior SoC Logic Design Engineer, you will be responsible for the development of logic design, register transfer level (RTL) coding, and simulation for systemic on-chip (SoC) designs. Your expertise will help integrate logic of IP blocks and subsystems into full chip designs, contributing significantly to both architecture and microarchitecture.

Experience Level

This position requires a significant level of experience, specifically over 8 years in IC/SoC Design and Micro Architecture, covering all phases of the logic development lifecycle.

Responsibilities

Your major responsibilities will include:

• Developing logic designs and performing quality checks from RTL to timing/power convergence.
• Applying various strategies and tools to optimize logic for power, performance, area, and timing goals.
• Collaborating with IP providers for integration and validation at the SoC level.
• Driving quality assurance compliance for effective IP-SoC handoff.
• Following secure development practices and addressing security within design.
• Reviewing verification plans to ensure correctness of design features and resolving failing RTL tests.

Requirements

Applicants must meet the following qualifications:

• A minimum of a BSEE/CE degree; an MS is preferred.
• Expertise in server microarchitecture, reset and clocking, power management, and integration.
• Experience in design-for-debug (DFD) and coherent fabric.
• Excellent communication skills and ability to work in a matrixed organization amidst ambiguity.

Education Requirements

Minimum educational requirement is a Bachelor’s degree in Electrical or Computer Engineering (BSEE/CE); Master’s degree is preferred.