Senior Silicon Design Verification Engineer

Role Summary

As a member of the Central Engineering Group, you will help bring to life cutting-edge designs. The focus of this role is to plan, build, and execute the verification of new and existing features for High Speed IO Protocol IPs (USB, PCIe, Ethernet, UFS) that are used in AMD’s product portfolio resulting in no bugs in the final design.

Experience Level

Level - Senior

Responsibilities

• Able to work well inside team/cross functional team
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.

Requirements

• Experience in IP level ASIC verification
• Experience in debugging firmware and RTL code using simulation tools.
• Experience in using UVM testbenches and working in Linux and Windows environments.
• Good understanding with UVM, Verilog, System Verilog, C, and C++.
• USB, UFS, Ethernet, PCIe, AXI knowledge is a plus.
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language (SVA, UVM scoreboard).
• Good working knowledge of SystemC and TLM with some related experience.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Over 5 years of digital IP verification with SV/UVM/formal verification or new methodology of the industry.

Education Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering.