Senior Silicon Design Verification Engineer

Role Summary

This position involves planning, building, and executing the verification of new and existing features for High Speed IO Protocol IPs such as USB, PCIe, Ethernet, and UFS within AMD’s product portfolio, aiming for a bug-free final design.

Experience Level

This role is suitable for candidates with over 5 years of experience in digital IP verification, particularly with SystemVerilog, UVM, and formal verification methodologies.

Responsibilities

• Collaborate effectively with cross-functional teams, including architects, hardware engineers, and firmware engineers to understand and verify new features.
• Create detailed test plan documentation, considering interactions between hardware, firmware, and software drivers.
• Estimate the time required for writing feature tests and making necessary adjustments to the testing environment.
• Develop directed and random verification tests.
• Diagnose and debug test failures, identifying the root causes and collaborating with RTL and firmware engineers to resolve issues.
• Review results against functional and code coverage metrics, adapting tests as needed to satisfy coverage requirements.

Requirements

Candidates should possess a strong understanding of IP-level ASIC verification processes, debugging experience with firmware and RTL code in simulation tools, and proficiency in UVM testbenches. Familiarity with operating in both Linux and Windows environments is required. A solid working knowledge of scripting languages (e.g., Perl, Ruby, shell) is preferred.

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.