Senior Signal Integrity Engineer - SerDes, Satellites (Starlink)

Job Title

Senior Signal Integrity Engineer - SerDes, Satellites (Starlink)

Role Summary

Lead signal integrity (SI) and power integrity (PI) work for Starlink satellite payload hardware across the full product lifecycle. The role sits on the Payload Engineering team and works cross-functionally with RF, antenna, ASIC, packaging, mechanical, thermal, software, supply chain, and production engineers.

Primary mission: define SI/PI architecture, simulation and verification flows, troubleshoot hardware in development and production, and establish signoff criteria and lab capabilities for high-speed and power-delivery subsystems.

Experience Level

Senior. Typical candidates have 5+ years of industry experience designing electronic hardware with experience in high-speed digital design and power integrity.

Responsibilities

Key responsibilities include:

• Specify, design, simulate, verify, qualify, and troubleshoot SI and PI for satellite hardware, including SerDes, optoelectronics, and high-speed memory interfaces.
• Architect PCB channel and PDN strategies; derive top-level specifications for PCB materials and channel subcomponents.
• Design and optimize transition structures across the channel (die bump to die bump) and drive component selection to meet PDN requirements.
• Collaborate with cross-functional teams during concept, package, and PCB design to ensure SI/PI goals are met.
• Develop and maintain simulation workflows, test methodologies, signoff criteria, and lab equipment requirements for SI/PI validation.
• Perform root-cause analysis and fixes for issues arising in PCB manufacturing, PCBA test, or satellite integration.

Requirements

Must-have qualifications and constraints:

• 5+ years of industry experience designing circuits, electronic products, or hardware.
• 2+ years using 3D EM simulation tools or high-speed digital channel simulators (e.g., CST, HFSS, ADS) or similar.
• 2+ years of research or industry experience with high-speed digital design or power integrity.
• Must meet ITAR eligibility: U.S. citizen, U.S. lawful permanent resident, refugee, asylee, or be able to obtain required U.S. Department of State authorizations.
• Ability to work extended hours or weekends when required; occasional travel may be needed.

Preferred (nice-to-have):

• Experience architecting and debugging DSP-based SerDes at 56–224 Gbps across package and PCB.
• Experience with high-bandwidth memory interfaces (DDR4, LPDDR5, GDDR, QSPI, eMMC).
• Experience designing PDNs for large processors, FPGAs, SoCs, or ASICs.
• Familiarity with low-loss laminates, high-volume PCB manufacturing, high-speed connectors, and EMI/EMC debugging.
• Proficiency in programming (Python, C/C++).

Education Requirements

Bachelor's degree in electrical engineering, computer engineering, or physics is required. Preferred qualifications include a Master’s or PhD in electrical or computer engineering with emphasis in electromagnetic theory, transmission line theory, wireline transceivers, or power integrity. Related technical degrees or equivalent practical experience are considered.

Additional Information

Compensation ranges provided: Level 1: $115,000 - $155,000; Level 2: $130,000 - $185,000. Actual level and base salary depend on experience, skills, and education. SpaceX is an Equal Opportunity Employer.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.