Senior Signal and Power Integrity Engineer

Job Title

Senior Signal and Power Integrity Engineer

Role Summary

Responsible for signal and power integrity analysis across chip, package, and PCB to support high-speed interfaces (for example NVLink, PCIe Gen6, DP2.1, 100GbE). Collaborate with package, PCB, and ASIC teams to develop PDN solutions, perform SI channel analysis, extract post-layout models, and correlate simulations with lab measurements.

Experience Level

Senior-level; requires 5+ years of industry experience.

Responsibilities

Key responsibilities:

• Develop SI/PI solutions for complex system designs and high-speed interfaces.
• Perform system-level PDN and power integrity simulations across interposers, packages, and PCBs.
• Conduct SI channel analysis and support specification development for interfaces such as DP2.1 and HDMI.
• Extract post-layout SI/PI models and support project review and sign-off.
• Collect, analyze, and correlate measurement data (VNA, TDR, oscilloscope) with simulation models.
• Automate simulation, data gathering, analysis, and visualization using tools such as MATLAB or JMP.
• Work cross-functionally to optimize package, PCB, and ASIC mixed-signal designs.

Requirements

Must-have:

• 5+ years of industry experience in signal and power integrity or related fields.
• Strong knowledge of electromagnetics, transmission line theory, via behavior, S/Y/Z parameters, and EMI implications.
• Hands-on experience with EM/SI tools such as ANSYS HFSS, Q3D, SIwave, and Cadence PowerSI.
• Experience with PDN evaluation using layout extraction and SPICE-based time-domain power-noise simulation.
• Die power-delivery modeling experience and familiarity with tools such as CSM/Redhawk or Raptor-X.
• Familiarity with voltage regulator modeling (Simplis/SPICE) and lab instruments (VNA, TDR, DSO).
• Experience correlating measurements with simulations and strong problem-solving skills.

Nice-to-have:

• Experience with MATLAB, Python, VBS, or C for simulation automation.
• Exposure to interface timing budgets, system modeling, and SI/PDN analysis flows in frequency and time domains.
• Familiarity with high-speed I/O design (clocking, transmitter/receiver design, equalization) and manufacturing variation impacts.
• Experience developing algorithms or methodologies to improve SI/PI/EMI modeling.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.