Senior SerDes System Architect

Role Overview

The position of Senior SerDes System Architect at Synopsys involves leading the design and verification of high-speed serial link systems, focusing on both analog and digital methodologies. You will work closely with interdisciplinary teams to innovate and implement cutting-edge technologies that align with industry demands.

Role Summary

In this role, you will leverage your expertise in SerDes system architecture, including communications theory and high-speed analog circuit design, to enhance the performance of silicon technology. Your contributions will be vital to the development of advanced chip designs utilized in high-performance applications.

Experience Level

The ideal candidate should possess at least 5 years of relevant experience in the field of electrical engineering, specializing in system architecture for SerDes implementation, alongside practical experience in related modeling techniques.

Responsibilities

• Collaboration with cross-disciplinary teams of analog and digital designers, enhancing design synergies.
• Involvement across all phases of project development, from architecture specifications to system-level testing.
• Execution of design verification methodologies across various communication protocols and environments.
• Expertise utilization to push technological advancements in high-speed analog CMOS design.
• Analysis of link budgets and facilitation of Tx/Rx equalization for high-speed links.

Requirements

• MSc or PhD in Electrical or Computer Engineering.
• 5 years of practical experience in SerDes system architecture.
• Strong foundation in communications concepts, particularly in equalization and noise filtering.
• Proficiency with C/Matlab/System Verilog for circuit modeling.
• Familiarity with scripting languages, preferably Python.
• Experience with high-speed analog CMOS circuits and link budget analysis.

Education Requirements

A Master's or PhD in Electrical or Computer Engineering is required for consideration