Senior RTL/FPGA Design Engineer

Role Overview

We are seeking a Senior RTL/FPGA Design Engineer to contribute to our design verification team. In this role, you will collaborate with architects, hardware engineers, and firmware engineers to ensure that the latest features are effectively implemented and tested. You will be a vital part of a team dedicated to delivering leading-edge technologies.

Role Summary

The position requires a proactive individual who excels in communication and teamwork, capable of working across multiple time zones. You are expected to apply your strong analytical and problem-solving skills while contributing innovative ideas to complex digital designs.

Experience Level

This role is suited for experienced professionals with a minimum of 5 years in RTL design and development, along with at least 3 years in FPGA Verilog design.

Responsibilities

Your key responsibilities will include:

• Collaborating with engineers to understand and verify new features.
• Creating specifications and documentation for requirements, design, and testing.
• Estimating implementation timelines and writing test cases.
• Debugging test failures and working with RTL and firmware engineers to resolve issues.
• Reviewing coverage metrics and modifying tests to meet requirements.

Requirements

The ideal candidate will have:

• A significant background in RTL design, particularly in a customer-facing context.
• Knowledge of technologies like PCIe, Ethernet, TCP/IP, etc.
• Experience with debugging RTL code and working with simulation tools.
• Familiarity with UVM testbenches and various operating environments.
• Proficiency in scripting languages such as Perl or Python.

Education Requirements

A Bachelor's or Master's degree in Electronics Engineering is required, with a strong track record of academic achievement.