Senior RTL Design Engineer - DDR Protocols

Role Summary

This role involves planning, designing, and validating new features for DDR IPs, while collaborating with various teams.

Experience Level

Candidate should possess a minimum of 5 years of relevant experience in digital design and RTL development, specifically with Verilog or SystemVerilog.

Responsibilities

Key responsibilities include:

• Designing and implementing firmware solutions for DDR memory calibration.
• Developing algorithms for reliable memory initialization under varying conditions.
• Creating validation plans for calibration firmware and executing system-level testing.
• Collaborating with engineering teams for hardware and system requirements alignment.
• Documenting calibration processes and ensuring compliance with standards.
• Staying updated on DDR technologies and proposing improvements.

Requirements

Candidates must meet the following requirements:

• B.E/M.E/M.Tech or B.S/M.S in Electrical or Computer Engineering.
• Experience with digital design using RTL languages.
• Knowledge of memory technologies including DDR4, DDR5, and JEDEC standards.
• Ability to work effectively in a team, with strong communication skills.
• Familiarity with version control systems is preferred.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required, along with at least 5 years of relevant experience.