Synopsys logo

Senior RTL Design Engineer

Synopsys
Full-time
On-site
Bhubaneswar, Odisha
Level - Senior

Role Overview

The Senior RTL Design Engineer will be pivotal in the ASIC Digital Design team, focusing on the design and implementation of RTL for various projects and ensuring the performance of digital circuits. The role demands proficiency in RTL design, verification, and collaboration across multiple teams to meet project milestones.

Experience Requirement

Candidates must have a proven track record in hardware design, ideally within ASIC environments. A deep understanding of digital design principles, along with experience in leading design projects, is essential. This position targets professionals who possess the expertise to elevate their work to a senior level.

Key Responsibilities

The main responsibilities include but are not limited to:

  • Designing complex RTL for digital signal processing, integrating various elements into a cohesive system.
  • Conducting intensive testing and verification to ensure functionality and performance meet specifications.
  • Collaborating closely with cross-functional teams, including verification engineers and other design specialists.
  • Mentoring junior engineers and providing insights for their professional development.
  • Staying abreast of the latest technologies and methodologies to enhance design quality.

Qualifications

To thrive in this role, candidates need to possess:

  • In-depth experience and understanding of RTL coding and synthesis.
  • Proficiency in tools such as Verilog or VHDL.
  • Dynamics of digital design flows and methodologies.
  • Prior involvement in ASIC design projects from conception to production.
  • Strong communication skills for effective collaboration within the team.

Education Requirements

A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field is required to fulfill the technical demands of this position.