Senior Principal Engineer, Advanced Package Technology

Job Title

Senior Principal Engineer, Advanced Package Technology

Role Summary

The Senior Principal Engineer will lead advanced packaging technology development and system-level package architecture for high-performance computing, AI accelerators, and networking solutions. The role sits in Marvell's Advanced Packaging R&D team and requires technical leadership across silicon, package, thermal, mechanical, and reliability domains.

Experience Level

Senior. Typical experience expectation: 10+ years with a Bachelor's degree, or 5+ years with a Master's or PhD. Leadership or technical lead experience is a strong plus.

Responsibilities

Primary responsibilities include defining package architecture, driving technology choices, and coordinating cross-functional development to move designs to volume readiness.

• Define system-level package architecture: chiplet topology, interposer/substrate scaling, PDN strategy, and thermal envelope.
• Own packaging technology roadmap for AI XPU, XPU-attach and switch platforms.
• Evaluate and architect technology choices: silicon/glass interposers, EMIB/bridge, hybrid bonding, fan-out, and 3D stacking.
• Lead co-design with silicon design, floorplanning, PDN modeling, and mechanical/thermal reliability teams.
• Work with vendors and OSATs/foundries to define equipment, process, material roadmaps, and validate manufacturability and yield.
• Drive package material selection, substrate stack-up definition, mechanical modeling, and reliability qualification to volume readiness.
• Support HBM integration strategies (HBM2E/HBM3/HBM3E) and memory integration approaches.
• Perform signal and power integrity trade-off analysis in partnership with SI/PI teams.
• Create proof-of-concept samples and protect IP derived from new packaging approaches.

Requirements

Must-have technical and professional requirements; education is summarized separately below.

• Significant hands-on experience with advanced package and substrate technologies, process and materials, component- and board-level reliability, warpage, and thermal management.
• Experience managing substrate/assembly material vendors, substrate manufacturers, OSATs, and foundries.
• Deep understanding of chip-package interactions and failure mechanisms at component and board level.
• Practical knowledge of signal integrity and power integrity considerations for multi-die and high-speed designs.
• Proven ability to manage cross-functional programs and influence stakeholders across architecture, silicon design, system engineering, and supply chain.
• Strong communication, presentation, documentation, and interpersonal skills; ability to work across time zones.
• Experience driving package qualification, reliability validation, and transitioning technologies to production.
• Nice-to-have: prior work on data center AI accelerators, networking or custom HPC silicon; experience setting roadmaps and supplier alignment; familiarity with CoWoS, EMIB, CPO, CPC, and advanced interconnects.

Education Requirements

Bachelor's degree in Mechanical Engineering, Materials Science, Electrical Engineering, or a related field with 10+ years of related professional experience; OR a Master's degree and/or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, or related fields with 5+ years of experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.