Senior Principal Digital IC Design Engineer

Job Title

Senior Principal Digital IC Design Engineer

Role Summary

Lead technical design and delivery of major digital IC subsystems or full-chip designs within Marvell's Custom Compute Solutions business unit. The role drives architecture and microarchitecture decisions, sets design methodology, and represents technical positions with customers, partners, and vendors.

The position focuses on high-performance ASIC/SoC work in areas such as AI, data movement, memory/storage, switching, and networking.

Experience Level

Senior — requires extensive senior-level experience; the posting specifies 15+ years of hands-on digital IC design experience.

Responsibilities

Primary responsibilities include technical leadership, architecture decisions, and mentoring within cross-functional teams.

• Provide recognized technical leadership for major digital IC subsystems or full-chip design disciplines.
• Drive architecture and microarchitecture trade-offs to meet performance, power, area, and schedule targets.
• Solve complex technical problems using independent judgment on methods and tools.
• Define and promote design methodology and best practices across teams.
• Act as technical sponsor in customer, partner, and vendor engagements.
• Mentor and guide engineers to improve delivery quality and knowledge sharing.

Requirements

Must-have technical skills, tools, and experience required for the role. Education qualifications are summarized separately below.

• Significant hands-on experience in digital logic design and verification for ASIC/SoC projects.
• Proven track record leading complex ASIC/SoC design efforts under schedule pressure.
• Strong knowledge of Verilog/SystemVerilog and digital verification methodologies.
• Familiarity with semiconductor ASIC design and verification flows and toolchains.
• Technical expertise in one or more domains: Ethernet, UA-Link, data-path security, networking/switching, AXI/APB, NOC fabrics, CPU subsystems, D2D, low-speed interfaces (I2C, I3C, UART, SPI), top-level logic (clocking/PLLs, reset strategies), debug, interrupts, fuses, and PHYs (Ethernet, PCIe, D2D).
• Experience with design-quality flows and tools such as lint, CDC, RDC, and functional verification (FEV).
• Strong analysis, problem-solving, teamwork, and communication skills.
• May require eligibility to access export-controlled information; candidates could be subject to export license review.

Education Requirements

BS or MS in Electrical Engineering or Computer Science is specified in the posting (BS/MS in EE/CS). The posting does not state alternative certifications; no explicit language about equivalent academic alternatives was provided.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.