Senior Principal Design Verification Engineer - FPGA (Sign-on Bonus)

Job Title

Senior Principal Design Verification Engineer - FPGA (Sign-on Bonus)

Role Summary

Lead design verification (DV) activities for FPGA-based signal processing and control functions in Electronic Warfare systems. Plan, architect, and develop verification environments and test plans; mentor junior engineers and lead small to medium DV teams.

Experience Level

Senior — 8+ years of relevant work experience (or equivalent experience).

Responsibilities

Primary responsibilities include creating and executing comprehensive verification solutions for FPGA designs and improving verification processes.

• Plan, architect, develop, and use configurable, self-checking testbenches in SystemVerilog, UVM/OVM and/or VHDL.
• Develop constrained-random, metric-driven test plans and verification strategies for FPGA signal processing and control functions.
• Collect and analyze coverage and metrics; use results to improve test effectiveness.
• Create reusable Verification IP to be shared across the organization.
• Lead small to medium DV teams, mentor junior engineers, and coordinate multi-site efforts.
• Drive process and methodology improvements and ensure tasks meet schedule and quality targets.

Requirements

Must-have technical skills, security and operational capabilities; preferred skills listed separately.

• Current U.S. security clearance (Secret) or eligible to obtain one.
• Experience planning, architecting, developing, and using constrained-random, self-checking testbenches in SystemVerilog, UVM, OVM, and/or VHDL.
• Experience with FPGA/ASIC design and verification tools (e.g., Mentor Questa or Cadence).
• Experience developing and implementing verification test plans and strategies.
• Proven ability to manage schedules, drive tasks to closure, and multitask across projects.
• Strong communication and technical documentation skills.
• Ability to work effectively in a multi-site or distributed environment.

Preferred (nice-to-have):

• Perl or Python scripting; C++ or Java.
• Familiarity with Git, Jira, BitBucket or similar tools.
• Digital Signal Processing experience; Matlab/Simulink.
• FPGA design experience and demonstrated reusable Verification IP development.
• Experience leading teams with accountability for cost, schedule, and quality; demonstrated mentoring skills.

Education Requirements

Bachelor's degree and 8+ years work experience, or equivalent practical experience. Field of study not specified.

About the Company

Company: BAE Systems

Headquarters: London, United Kingdom

Global defense, aerospace and security company delivering products and services for air, land and naval forces, advanced electronics, cyber and intelligence solutions, and space and mission systems for government and commercial customers.