Senior Principal Design Verification Engineer - FPGA

Job Title

Senior Principal Design Verification Engineer - FPGA

Role Summary

Lead the planning, architecture, development, and execution of FPGA design verification environments for electronic warfare and signal-processing systems. Work with small to medium teams, mentor junior engineers, and improve verification processes and reusable verification IP.

This is an on-site, hands-on engineering role focused on delivering robust verification strategies and measurable coverage-driven results.

Experience Level

Senior — role title indicates senior/principal level. Posting requests 8+ years of related experience (or equivalent experience).

Responsibilities

Key duties include designing verification environments, implementing tests, driving coverage, and leading engineers.

• Plan, architect, develop, and use configurable, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL.
• Develop constrained-random, metric-driven test plans and verification strategies for FPGA signal-processing and control functions.
• Collect and analyze coverage metrics and refine testcases to improve verification effectiveness.
• Create reusable Verification IP for cross-organization use.
• Lead and mentor small-to-medium DV teams and junior engineers across multiple U.S. locations.
• Drive process and methodology improvements for verification flow.
• Coordinate with subject-matter experts to validate verification approaches and requirements.
• Manage multiple projects, prioritize tasks, and meet schedule commitments.

Requirements

Must-have technical skills, security, and interpersonal capabilities required to perform the role.

• Current U.S. security clearance (Secret) or eligibility to obtain one.
• Proven experience developing constrained-random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL.
• Experience with FPGA/ASIC design and verification tools (e.g., Mentor Questa or Cadence).
• Proven ability to manage schedules, drive tasks to closure, and support multiple projects concurrently.
• Strong written and verbal communication and documentation skills.
• Experience developing and implementing verification test plans and coverage-driven strategies.
• Ability to work effectively in a multi-site or distributed environment.

Nice-to-have:

• Perl or Python scripting.
• C++ or Java experience.
• Familiarity with Git, Jira, Bitbucket.
• Digital Signal Processing and MATLAB/Simulink experience.
• Working knowledge of VHDL and FPGA design experience.
• Experience creating reusable Verification IP, leading teams, and driving process improvements.

Education Requirements

Bachelor's degree plus 8+ years of relevant work experience, or equivalent practical experience. (Field of study not specified.)

About the Company

Company: BAE Systems

Headquarters: London, United Kingdom

Global defense, aerospace and security company delivering products and services for air, land and naval forces, advanced electronics, cyber and intelligence solutions, and space and mission systems for government and commercial customers.