Senior/Principal Design Verification Engineer

Role Summary

The Senior/Principal Design Verification Engineer will engage in pre-silicon RTL Verification activities focused on Memory Controller SoftIP development, with an emphasis on advanced DDR, HBM, and GDDR DRAM controller technologies. This role is based in Hillsboro, Oregon, and involves close collaboration with a team dedicated to achieving high standards in performance and reliability.

Experience Level

This position is suitable for candidates with a minimum of 7 years of experience, ideally with a strong background in HDL logic Design-Verification.

Responsibilities

• Develop and maintain testbenches and test sequences for new controller technologies and features.
• Plan functional coverage, write coverage items, and augment test suites to meet coverage goals.
• Create, monitor, and debug regression tests, ensuring the integrity of the controller RTL design.
• Enhance and support scripting capabilities within the Verification environment.

Requirements

Applicants should possess fluency in System Verilog testbench and Verilog/System Verilog RTL design. Familiarity with DDR DRAM technology is preferred, alongside experience in Python and TCL scripting languages.

Education Requirements

A Bachelor's Degree or higher in Electrical Engineering or Computer Science is required for this position.