Senior Principal Design Engineer

Role Summary

The Senior Principal Design Engineer will contribute to the development and verification of complex electronic design systems within Cadence. This role requires a deep understanding of design verification, particularly in System Verilog (SV) and Universal Verification Methodology (UVM).

Experience Level

This position is targeted towards a seasoned professional with a minimum of 12 years of experience in design verification, showcasing expertise in the field.

Responsibilities

• Lead design verification projects from initial concept through to verification closure.
• Develop and implement functional verification environments for complex designs.
• Create comprehensive test plans and perform environment planning as per project requirements.
• Utilize strong hands-on expertise in UVM and System Verilog for coding verification environments.
• Oversee verification processes, ensuring adherence to quality standards and timelines.
• Engage in IP verification, particularly involving memory IPs such as DDR, HBM, and GDDR.

Requirements

A bachelor's or master's degree in Electrical/Electronics/VLSI is required for this position, alongside a proven track record in design verification and coding practices.

Education Requirements

Applicants must hold a BE/BTech/ME/MTech degree in Electrical Engineering, Electronics, or VLSI.