Senior Physical Design Methodology Engineer, PPA Fusion Compiler
NVIDIAJob Title
Senior Physical Design Methodology Engineer, PPA Fusion Compiler
Role Summary
Join NVIDIA's Networking Silicon engineering team to develop physical-design methodologies and ML-driven tools that improve power, performance, and area (PPA) for high-speed communication SoCs and GPUs. The role spans place-and-route flows, timing/IR/EM convergence, power and clock distribution, and backend verification across multiple projects.
Base salary ranges provided by the employer: $168,000 - $264,500 (Level 4) and $196,000 - $310,500 (Level 5).
Experience Level
Senior — typically requires 10+ years of relevant physical design engineering experience.
Responsibilities
Primary responsibilities include:
- Develop physical-design methodologies for implementation of GPUs and SoCs to improve PPA.
- Design and integrate ML-based algorithms and toolchains for PPA analysis, checks, and closure.
- Develop flows and methodologies for place-and-route, timing analysis, IR/EM convergence, and power/noise analysis.
- Work on floorplan, power and clock distribution, chip assembly, and back-end verification across projects.
- Perform data-driven analysis and create algorithmic solutions to detect and improve PPA issues.
- Implement and maintain automation and scripting to support P&R and PPA improvements.
- Collaborate with cross-functional teams to achieve timing, EM/IR, and manufacturability convergence.
Requirements
Must-have qualifications:
- 10+ years of physical design engineering experience with hands-on development of ML-based solutions.
- Proven record implementing ML-based solutions in chip design or EDA flows.
- Experience with floorplanning, clock and power distribution, place-and-route, integration and verification.
- Strong background in hierarchical/top-down design, budgeting, timing and physical convergence.
- Familiarity with design-for-yield/manufacturability, EM/IR closure, and thermal management.
- Proficient with industry place-and-route and analysis tools and capable of extensive scripting to automate checks and improve PPA.
Nice-to-have:
- Experience with high-speed networking device design and advanced process nodes.
- Experience across packaging, chip assembly, or multi-die integration.
Education Requirements
MS in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent practical experience.
NVIDIA is an equal opportunity employer.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
