Senior Physical Design Engineer - Neuromorphic Computing

Job Title

Senior Physical Design Engineer - Neuromorphic Computing

Role Summary

Senior physical design engineer on Intel's neuromorphic silicon team responsible for physical integration, floorplanning, timing closure, and package/die-level requirements for next-generation neuromorphic AI chips and chiplets. The role focuses on delivering silicon through hands-on implementation, verification, and cross-team coordination.

Experience Level

Senior — requires substantial hands-on physical design experience. The posting specifies 6+ years with a Bachelor's or 4+ years with a Master's.

Responsibilities

Primary responsibilities include delivering chip- and block-level physical design and closure, and integrating chiplets and advanced packaging.

• Translate system specifications into package- and die-level requirements.
• Architect full-chip floorplans and define partition-level floorplans with macro/pin placements and keep-outs.
• Define timing constraints with RTL teams; run synthesis and place-and-route trials; resolve timing, EM/IR, LVS and DRC violations.
• Run back-annotated simulations (VCS+SDF) and iterate to meet power/performance targets.
• Create scripts and tool flows to drive synthesis and physical design tools for low-power, high-performance designs.
• Lead block- and chip-level closure activities to meet performance, power, and area KPIs.

Requirements

Must-have technical experience and skills (minimum qualifications). Degree details are listed under Education Requirements below.

• Hands-on physical design experience delivering multiple silicon tape-outs.
• 6+ years setting up floorplans, defining timing and power constraints, and iterating through synthesis/place-and-route to meet product KPIs.
• 6+ years scripting experience (Perl, TCL, Python, or similar).
• 4+ years debugging FEV and RV reports and planning ECOs.
• 2+ years experience in chiplet integration and/or advanced packaging.
• 1+ year experience using AI tools to set up tool flows, debug, or improve productivity.
• Strong problem-solving, ability to coordinate across RTL, physical design, and packaging teams.

Nice-to-have / preferred

• Static timing experience with interfaces such as SerDes and UCIe.
• Experience with Cadence Virtuoso and Synopsys tool flows (Fusion Compiler, PrimeTime, StarRC, SiliconSmart, VCS).
• EDA/CAD software development experience (Java or C++).
• Experience with asynchronous architectures and circuits.

Education Requirements

Minimum: Bachelor's degree plus 6+ years of hands-on physical design experience, or Master's degree plus 4+ years of hands-on physical design experience. Experience may be obtained through a combination of degree, research, internships, or relevant industry roles. (No specific field of study explicitly mandated in the posting.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.