Senior Physical Design Engineer (Lead)

Job Title

Senior Physical Design Engineer (Lead)

Role Summary

Responsible for block- and subsystem-level physical implementation of FPGA/SoC designs, driving floorplan, placement, CTS, routing, ECOs and sign-off to meet performance, power, area (PPA) and schedule targets. Works with RTL, architecture, DFT, CAD/EDA and verification teams to resolve implementation challenges and support successful tape-out.

Experience Level

Senior — typically requires 4+ years of industry experience in physical design, physical implementation, or SoC/ASIC backend design.

Responsibilities

Deliver assigned physical design tasks and support integration through to sign-off.

• Execute physical implementation activities: floorplanning, power planning, placement, clock tree synthesis (CTS), routing, ECOs, extraction, and sign-off.
• Perform static timing analysis and timing closure; identify critical paths and resolve timing issues.
• Analyze and optimize designs for performance, power, and area (PPA).
• Review and debug implementation issues related to placement, congestion, clocking, routing, timing, and constraints.
• Support physical verification (DRC, LVS) and resolve sign-off issues.
• Develop basic automation and scripts to improve productivity and automate repetitive tasks.
• Support block-level integration: constraints, pin placement, timing interfaces.
• Participate in design reviews, documentation, and continuous improvement of flows and methodologies.

Requirements

Key must-have skills and preferred additions.

• Must-have: 4+ years hands-on experience in digital ASIC and/or SoC physical design, including floorplanning, placement, CTS, routing, ECO implementation, and physical sign-off.
• Must-have: Experience with industry EDA physical design and sign-off tools (for example Synopsys IC Compiler II, Fusion Compiler, PrimeTime, Cadence Innovus, or equivalent).
• Must-have: Strong static timing analysis and timing-closure skills; able to analyze timing reports and resolve setup/hold violations.
• Must-have: Familiarity with physical design constraints (clocks, timing constraints, placement constraints, design rules) and debugging implementation issues (congestion, routing, timing, DRC/LVS).
• Must-have: Ability to collaborate effectively with RTL, architecture, DFT, CAD/EDA and cross-functional teams during implementation.
• Must-have: Basic scripting/automation skills (Tcl, Python, Perl, Shell or similar).
• Nice-to-have: Experience with advanced process nodes (16nm, 10nm, 7nm, 5nm), FPGA architectures, low-power design, power integrity (IR drop/EM), hierarchical/full-chip flows, or AI/ML-assisted physical design tools.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline is required. A Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline is preferred.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.