Senior Physical Design Engineer

Job Title

Senior Physical Design Engineer

Role Summary

Join the Physical Design organization to implement custom IP and SoC designs from RTL through GDSII for next-generation FPGA products. The role focuses on physical implementation, timing closure, power optimization, and design signoff while collaborating with RTL, verification, DFT, timing, and CAD teams.

Experience Level

Senior — typically 6+ years of hands-on ASIC/SoC physical design experience as specified in the minimum qualifications.

Responsibilities

Deliver and sign off production-quality physical designs and improve physical design flows and automation.

• Implement physical design from RTL through GDSII to produce manufacturing-ready databases.
• Execute synthesis, floorplanning, place-and-route, CTS, STA, power and clock distribution, and reliability analysis.
• Perform physical verification and signoff tasks: formal equivalence, static timing, DRC/LVS/ERC, and power integrity checks.
• Analyze signoff results, identify violations, and develop corrective solutions.
• Optimize designs for power, performance, frequency, and area (PPA).
• Apply expertise in clock design, timing closure, placement, routing, DFT implementation, and multi-voltage domain support.
• Collaborate with cross-functional teams (architecture, RTL, timing, DFT, verification, CAD) during the design cycle.
• Contribute to the development and continuous improvement of methodologies and automation for physical design flows.

Requirements

Required technical experience and tool knowledge to perform the responsibilities below.

Must-have

• 6+ years of hands-on digital ASIC or SoC physical design implementation, including RTL-to-GDSII flows.
• 6+ years experience with synthesis, floorplanning, place & route, and clock tree synthesis (CTS).
• 6+ years performing static timing analysis (STA) and timing closure.
• 4+ years experience with physical verification and signoff methodologies (DRC, LVS, ERC).
• 4+ years using industry-standard EDA tools such as Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, or equivalent.
• 3+ years optimizing designs for power, performance, and area (PPA).
• 2+ years supporting designs with multiple voltage or power domains.
• Strong analytical, debugging, collaboration, and communication skills.

Nice-to-have

• Experience with advanced process nodes (7nm, 5nm, 3nm or similar).
• Experience with DFT-aware physical design flows, scan-chain optimization, and large-scale SoC or FPGA architectures.
• Experience in physical-design automation and scripting (Python, Tcl, Perl, Shell).
• Familiarity with power integrity (IR drop), electromigration (EM), and signal integrity analysis.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. Preferred: Master’s degree in a related technical field. (Equivalent practical experience may be considered where stated by the employer.)

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.