Senior Physical Design Engineer

Job Title

Senior Physical Design Engineer

Role Summary

Join Microsoft's Compute Silicon & Manufacturing Engineering (CSME) within Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) to deliver physical design for large SoC blocks used in Microsoft cloud infrastructure. The role owns RTL-to-GDS implementation and all physical-design signoff stages.

This is an individual contributor role working cross-functionally with CAD, RTL/design, architecture, power/performance, and technology teams. The position expects in-office collaboration on a hybrid schedule (3 days/week onsite as listed by the employer).

Experience Level

Senior — the role targets experienced engineers. Preferred: 7+ years of semiconductor design experience; see Education Requirements for degree/experience equivalencies.

Responsibilities

The engineer will drive technical execution and influence flows, tools, and methodology.

• Execute end-to-end physical design from synthesis through place-and-route to GDS production.
• Deliver and sign off timing closure, physical verification, EMIR, formal equivalence, and low-power verification for medium-to-large SOC blocks.
• Design and implement clock construction and clock tree synthesis (CTS) strategies for high-speed designs.
• Perform RTL-to-GDS implementation, including floorplanning, partition P&R, extraction, and timing signoff.
• Optimize designs for power, performance, and area (PPA) using data-driven analysis and methodology tuning.
• Collaborate with CAD/PD flow, RTL/design, DFT, architecture, power/performance, technology, and foundry partners.
• Drive methodology exploration and PD tool/flow improvements; flag and resolve PD tool/TFM issues.
• Communicate project status, planning, and technical decisions clearly to cross-functional teams.

Requirements

Key technical skills, screening requirements, and preferred experiences.

• Must-have: Proven hands-on experience across synthesis, floorplanning, place-and-route, extraction, static timing analysis and timing signoff, physical verification, EMIR signoff, formal equivalence, and low-power verification.
• Must-have: Deep experience with clock construction strategies and CTS for high-speed designs.
• Must-have: Demonstrated ability to own PD execution for medium-to-large SOC blocks and deliver production-quality results.
• Must-have: Strong collaboration and communication skills to work across CAD, RTL/design, architecture, power, and technology teams.
• Must-have: Ability to pass Microsoft Cloud Background Check and meet export-control eligibility requirements (citizenship or residency documentation may be required).
• Nice-to-have: Production silicon tape-outs in advanced foundry nodes and extensive low-power SOC methodology experience.
• Nice-to-have: Experience influencing PD tools, flows, and methodology through data-driven optimization; prior work with PD flow/CAD teams.
• Nice-to-have: Strong problem-solving and data analysis skills; experience with automation, scripting, or CAD tool development.

Education Requirements

One of the following or equivalent experience: Doctorate (PhD) in Electrical Engineering, Computer Engineering, Computer Science, or related field + 1+ year technical experience; OR Master’s degree in those fields + 4+ years technical experience; OR Bachelor’s degree in those fields + 5+ years technical experience; OR equivalent practical experience. Fields explicitly referenced: Electrical Engineering, Computer Engineering, Computer Science, or related technical disciplines.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.