Senior PD Methodology Engineer

Role Summary

We are looking for a seasoned Circuit Design & Analysis Engineer to join the Machine Learning Acceleration (MLA) team responsible for developing the Inferentia and Trainium SOCs. This position involves close collaboration with cross-functional teams to enhance silicon yield and performance.

Experience Level

Ideal candidates will have at least 8 years of experience in ASIC implementation, synthesis, static timing analysis (STA), and physical design in deep sub-micron nodes, specifically 16nm or smaller.

Responsibilities

The primary responsibilities for this role include:

• Designing and implementing custom cells and intellectual property (IP).
• Developing and executing characterization flows for custom cells/IP.
• Owning the integration and post-silicon qualification of various IPs, including PLL, PCIE, UCIE, and HBM.
• Automating analysis and report generation through scripting.
• Creating test plans and performing laboratory measurements to corroborate simulation data.
• Collaborating with physical design, product, and hardware engineers to identify and resolve issues.

Requirements

The following qualifications are required:

• BS degree in computer science, computer engineering, or a related field.
• Proven experience with physical design teams on optimized ASIC design.
• Proficiency in Python or Perl programming.
• Familiarity with sign-off activities including IR/EM, physical verification, and timing closure.
• Expertise in circuit analysis using tools like SPICE or SPECTRE.
• Strong understanding of interconnect and transistor fundamentals in deep sub-micron processes.

Education Requirements

While a Bachelor's degree is required, a Master's or Ph.D. in Electrical Engineering or a related field is preferred.