Senior Manager - SOC Verification

Job Title

Senior Manager - SOC Verification

Role Summary

Senior verification engineer and manager in the dsPIC Microcontroller Business Unit responsible for ensuring functional integrity of next-generation 32-bit MCU SoCs. Lead verification strategy, develop verification environments and suites, debug full-chip issues, and mentor verification engineers across a global team.

Experience Level

Senior — requires 10+ years of SoC verification experience.

Responsibilities

Define and execute verification plans for complex MCU SoCs and manage verification activities across teams.

• Lead development of testbenches and verification environments using UVM/SystemVerilog.
• Design and run coverage-driven verification and large regression suites at module and full-chip level.
• Perform RTL and gate-level verification, analyze GLS results and timing violations, and coordinate with STA teams to resolve issues.
• Develop functional safety tests, fault-injection simulations, and coverage analysis.
• Debug complex system-level and full-chip issues, including interactions between digital and mixed-signal components.
• Define and implement formal verification for properties and connectivity using tools like JasperGold or VC Formal.
• Mentor and develop junior engineers; promote adoption of advanced verification techniques and automation.
• Collaborate with architecture, design, STA, and post-silicon teams to align verification and validation strategies.

Requirements

Core technical skills and domain experience required for the role.

Must-have:

• Expert-level SystemVerilog and UVM experience for testbench and verification development.
• Strong background in SoC verification, including coverage-driven verification and regression management.
• Direct experience verifying ARM-based SoCs (Cortex-M) and proprietary RISC architectures.
• Deep knowledge of MCU peripherals (DMA, timers, ADC/DAC interfaces, security modules) and MCU-specific verification needs.
• Experience with STA, gate-level simulation analysis, and resolving timing violations.
• Formal verification experience (property and connectivity checking) with tools such as JasperGold or VC Formal.
• In-depth understanding of AMBA protocols (AHB, APB, AXI).
• Proven ability to debug full-chip issues and integrate module-level testbenches into full-chip verification.
• Experience leading teams and mentoring engineers.

Nice-to-have:

• Gate-level simulation and power-aware verification experience.
• Analog mixed-signal (AMS) simulation exposure and post-silicon validation experience.
• Familiarity with functional safety standards such as ISO 26262 for automotive MCUs.

Education Requirements

Bachelor of Engineering in Electronics/Electrical or Computer Science (BE/BTech) with strong digital design fundamentals is specified.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.