Senior Manager, R&D Engineering - Embedded Memory IP

Job Title

Senior Manager, R&D Engineering - Embedded Memory IP

Role Summary

Lead a cross-functional engineering team responsible for embedded memory IP (SRAM, register files, TCAM, ROM) development across architecture, circuit design, layout, verification, characterization, and model generation for advanced FinFET nodes.

Drive technical decisions, schedule execution, and cross-site collaboration to deliver production-ready memory compilers used in high-volume SoCs.

Experience Level

Senior - 10+ years of hands-on experience in embedded memory design and delivery.

Responsibilities

You will manage technical and program execution across the full memory IP development cycle and coordinate with internal teams and customers.

• Lead bit-cell analysis, architecture definition, circuit design, layout planning, verification, characterization, and model generation for memory IP.
• Drive SRAM, register file, TCAM, and ROM compiler development, optimizing power, performance, area, and yield for advanced FinFET processes.
• Oversee schematic entry, transistor-level simulation, layout interactions, and interfaces with CAD and physical verification teams.
• Design and validate low-power, area-efficient circuits resilient to deep-submicron and FinFET process variations.
• Prioritize workloads, manage multiple concurrent projects, and resolve schedule or quality risks.
• Collaborate with customers and internal stakeholders to align on technical solutions and deliverables.
• Identify gaps in existing flows, implement process improvements, and ramp projects to completion on aggressive timelines.

Requirements

Must-have technical skills, leadership experience, and practical tool proficiency for delivering memory IP at advanced nodes.

• 10+ years hands-on experience in embedded memory design covering architecture, circuit design, physical implementation, compiler automation, characterization, and model generation.
• Deep expertise in SRAM and register file architectures, sense amplifiers, write drivers, decoders, and bit-cell design.
• Direct experience with memory IP design in FinFET process nodes, including variation-aware design, leakage management, and yield optimization.
• Proficiency in scripting for flow automation and characterization (Perl and Python).
• Solid grounding in CMOS fundamentals, RC analysis, digital and analog circuit principles applied to memory design.
• Proven ability to lead engineering teams, manage multi-project priorities, and deliver complex IP in a cross-site, multi-discipline environment.
• Excellent problem-solving under schedule pressure and ability to communicate trade-offs to technical and non-technical stakeholders.

Education Requirements

Required: BE/B.Tech or ME/M.Tech/MS in Electrical and Electronics Engineering.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.