Senior Manager, Analog & Mixed-Signal Design Engineering

Job Title

Senior Manager, Analog & Mixed-Signal Design Engineering

Role Summary

Lead a team in Intel's Hard IP and Test Chip Development group to deliver analog and mixed-signal IP and silicon solutions for high-speed connectivity, chiplet architectures, and advanced interconnect technologies. The role covers architecture, design, silicon validation, and production readiness across client, data center, AI, and foundry products.

This is a high-visibility leadership role focused on technical direction, cross-functional coordination, program execution, and growing engineering talent.

Experience Level

Senior-level — typically requires 9+ years of relevant engineering experience plus significant leadership experience (see Requirements for details).

Responsibilities

Accountable for technical leadership, program execution, and team development to deliver production-ready analog IP.

• Lead development and delivery of analog and mixed-signal IP (ADCs, DACs, phase interpolators, voltage regulators, clocking circuits, and other analog building blocks).
• Drive architecture reviews, design execution, verification, silicon bring-up, validation, and product readiness.
• Define execution strategies; manage schedules, resources, risks, dependencies, and deliverables across concurrent programs.
• Recruit, coach, mentor, and retain engineering talent; develop future technical and organizational leaders.
• Partner with architecture, design, validation, physical design, layout, product engineering, manufacturing, and program management teams.
• Coordinate with geographically distributed teams to align priorities and meet milestones.
• Promote engineering innovation through automation, process optimization, and AI-assisted methodologies.
• Provide data-driven reporting to support decisions and drive successful business outcomes.

Requirements

Minimum technical and leadership experience required; preferred qualifications noted below.

• 9+ years of relevant engineering experience.
• 6+ years in people leadership, technical leadership, project leadership, or management within a matrixed organization.
• 8+ years delivering analog or mixed-signal IP from concept through silicon validation and product deployment.
• 7+ years of experience with analog design fundamentals (noise, jitter, matching, stability, linearity, performance optimization).
• 7+ years of silicon bring-up, post-silicon validation, and lab debug of analog circuits.
• Experience managing analog IP design teams and driving execution on complex, high-impact programs.
• Preferred domain experience: PLL, CDR, CTLE, DFE, ADC, transmitter or receiver design; familiarity with high-speed serial IO (PCIe/CXL, USB Type C) and die-to-die technologies (UCIe).
• On-site role with expected office presence of at least 4 days per week.
• Position is not eligible for immigration sponsorship.

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field (posting specifies Bachelor's with 9+ years of experience). Preferred: Master's degree in Electrical/Electronics Engineering or a related field. The posting does not specify certifications or explicit language allowing equivalent experience in place of a degree.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.