Senior Manager, AMS Design Verification

Role Summary

The Senior Manager, AMS Design Verification leads the design verification (DV) function for complex gate drivers, ensuring efficient collaboration with design and verification teams to achieve first-pass silicon success and performance goals.

Experience Level

Senior level position with 15+ years of experience in mixed-signal IC design and/or verification.

Responsibilities

Key responsibilities include:

• Leading the DV function by defining test cases and coverage.
• Creating automation to run the DV suite before tape-out.
• Collaborating with design and verification teams.
• Integrating design verification processes for optimal results.
• Creating accurate Verilog or SystemVerilog models for complex analog blocks.

Requirements

Must-have qualifications include:

• 15+ years of experience in mixed-signal IC design and/or verification.
• Proficiency in Verilog, SystemVerilog, VerilogAMS, and UVM.
• Strong understanding of analog circuits, digital design processes, and top-level integration.
• Excellent simulation debugging skills.
• Proficient in Unix environment and shell scripting with knowledge of Python.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.