Senior Lead RTL Design Engineer

Advanced Micro Devices Inc is seeking a Senior Lead RTL Design Engineer in Bangalore, India.

Role Summary

The focus of this role is to microarchitect, design and deliver data fabric IP RTL. This includes new and existing features and components for AMD’s data fabric IP, working closely with verification to ensure design quality.

Experience Level

Level - Senior

Responsibilities

• Digital design implementation and micro-architecture of components of the Infinity Data Fabric.
• Micro-architecture and RTL coding in Verilog/SystemVerilog of Data fabric components and its features as the fabric scales for server, data center application systems.
• Responsible for resolution of inter IP integration issues.
• Perform design flow quality checks - Lint, CDC, RDC and others.
• Timing closure including timing constraints, synthesis, and logic-depth reduction.
• Design area optimizations.
• Implement low power design techniques, including UPF.

Requirements

• 12 years of working experience in ASIC design.
• Proficiency in Verilog/SystemVerilog RTL.
• Experience in full IP design cycle, including requirements definition, architecture and microarchitecture specification.
• Active knowledge of ASIC design quality flows.
• Knowledge of cache coherency and/or fabric/NOC design is a plus.
• Low power analysis and design experience.
• Familiarity with version control systems such as Perforce and Git.

Education Requirements

• Bachelors or Masters degree in Computer Engineering or Electrical Engineering.