Senior Lead - RTL Design Engineer

Role Summary

This position involves working on next-generation technology integrated within AMD Microprocessors, focusing on Servers, Personal Computers, Graphics Cards, and VR devices. The role is within the UMC FEINT/Implementation team, focusing on high-speed designs exceeding 2G.

Experience Level

Minimum of 12 years of relevant work experience in ASIC RTL Design and Synthesis is required.

Responsibilities

The core duties for this role include:

• Performing logical and physical synthesis of IP blocks.
• Analyzing and verifying design specifications for functionality, performance, and area.
• Defining synthesis design constraints and resolving timing analysis (STA) issues.
• Conducting timing analysis and offering solutions for timing violations.
• Completing design quality checks and data quality assessments.
• Collaborating with RTL engineers to troubleshoot timing issues.
• Leading the evaluation of new tools and refining methodologies.
• Developing and improving automatic ECO generation scripts for timing closure.
• Implementing low-power optimizations and UPF.

Requirements

The ideal candidate should possess:

• Extensive experience with Synopsys tools for ASIC synthesis and timing constraints.
• A strong foundation in Timing analysis and CDC.
• Expertise in CDC/RDC/LINT closure processes.
• Familiarity with power intent definitions and implementations (UPF).
• Knowledge of low power optimization techniques.
• Proficiency in Verilog, System Verilog, and scripting languages such as Perl/TCL/Makefile.
• Experience in power analysis tools like Power Artist and PTPX.
• Knowledge of LEC and LP signoff tools.
• Understanding of VLSI front-end design processes.
• Capable communication skills for effective teamwork across global teams.

Education Requirements

A Bachelors or Masters degree in Computer Engineering or Electrical Engineering is required.