Senior Layout Engineer – DPG Layout

Job Title

Senior Layout Engineer – DPG Layout

Role Summary

Design and implement block-level analog, mixed-signal, and custom digital layouts and support integration at the chip level. The role focuses on producing manufacturable, high-quality block layouts and collaborating with design, verification, CAD, and senior layout engineers to meet schedule and quality targets.

Work includes layout execution, verification closure, automation of repetitive tasks using scripting and prompt-based AI tools, and mentoring less-experienced engineers.

Experience Level

Senior — requires at least 3+ years of practical experience in analog/custom layout design in advanced CMOS processes.

Responsibilities

Primary responsibilities for this role include:

• Execute block-level layout for analog, mixed-signal, and custom digital blocks with attention to design intent, manufacturability, and turnaround time.
• Perform layout verification tasks including DRC, LVS, antenna, yield, and quality checks and own verification closure for assigned blocks.
• Use and develop scripts (SKILL/Python/TCL) and prompt-based AI tools to automate repetitive layout and verification tasks and improve consistency.
• Support custom and digital layout integration, accelerate ECOs and alignment using semi-custom tools, and assist full-chip integration.
• Collaborate with Design, Verification, CAD, and senior layout engineers to communicate status and risks and to resolve issues.
• Review sub-block layouts from junior engineers and share best practices and techniques within the team.

Requirements

Must-have technical skills and experience (concise):

• Minimum 3+ years of hands-on analog/custom layout experience in advanced CMOS processes.
• Proficiency with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS and ownership of verification/closure for assigned blocks.
• Experience laying out critical analog/mixed-signal blocks such as temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, and charge pumps.
• Strong understanding of layout fundamentals: matching, symmetry, electromigration, latch-up, IR-drop, coupling, crosstalk, and parasitic effects.
• Ability to translate design constraints into robust, manufacturable layouts and understand layout impact on speed, capacitance, power, and area.
• Experience applying or developing AI-driven automation and AI-assisted methodologies for layout and verification tasks.
• Strong problem-solving skills for physical layout verification and debug.

Nice-to-have:

• Exposure to memory layout environments (DRAM, SRAM, CAM, OTP) is desirable.

Education Requirements

Bachelor's and master's degrees specified: B.Tech in Electronics, Electronics & Communication, or VLSI Engineering; M.Tech in VLSI Design, Microelectronics, or Electronics Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.