Senior Layout Design Engineer

Role Overview

The Senior Layout Design Engineer will be responsible for designing and integrating memory leafcells and standard cell layouts. This role requires expertise in FinFET technology, physical verification, and optimizing layouts for performance metrics such as speed, area, and power.

Experience Level

This position requires a candidate with at least two years of experience in custom, standard cell, or memory layout design. Proficiency in various design and verification tools is essential.

Key Responsibilities

The main responsibilities for this position include:

• Designing and integrating memory leafcells and standard cell layouts.
• Optimizing layouts focusing on performance parameters such as speed, area, and power consumption.
• Running and debugging design rule checks (DRC), layout versus schematic (LVS) checks, and electrical rule checks (ERC).
• Collaborating effectively with circuit and verification engineers.
• Utilizing Custom Compiler and ICV tools for design tasks and verification processes.
• Automating design tasks using scripting languages including Perl, Shell, or TCL.

Essential Requirements

Applicants should possess the following qualifications:

• A minimum of 2 years in custom, standard cell, or memory layout design.
• Experience with FinFET technology, along with DRC, LVS, ERC, and boundary conditions.
• Proficiency in Custom Compiler and ICV tools.
• Strong skills in scripting with Perl, Shell, or TCL.
• A Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related discipline.
• Excellent troubleshooting and optimization capabilities.

Education Requirements

A Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field is required for this role.