Senior IP Verification Engineer

Role Summary

The Senior IP Verification Engineer is responsible for planning, developing, and executing the verification of AMD’s ASIC and FPGA SoCs. This entails ensuring that both new and existing features are bug-free and meet the required functional specifications.

Experience Level

This position requires significant experience, specifically 7+ years with a Bachelor’s degree or 5+ years with a Master’s degree in Computer or Electrical Engineering.

Responsibilities

The key responsibilities include:

• Working within a geographically distributed team to verify cutting-edge ASIC and FPGAs.
• Creating test plans, implementing test benches, and developing test cases to achieve full functional coverage.
• Conducting regression testing and enhancing verification infrastructure.
• Designing and executing both directed and random verification tests.
• Debugging test failures, identifying root causes, and collaborating with RTL and firmware engineers to resolve issues.
• Evaluating functional and code coverage metrics, and adjusting tests to meet coverage goals.
• Collaborating with design, software, and architecture teams for effective verification.

Requirements

The ideal candidate will have:

• Proficiency in IP-level FPGA and ASIC verification.
• Experience with PCIe, CXL or other IO protocols is a plus.
• Knowledge of Verilog/SystemVerilog, and scripting languages such as Perl or Python.
• Hands-on experience with SystemVerilog and UVM.
• Experience in developing UVM-based verification test benches.
• A solid understanding of design flow, verification methodologies, and computational logic design.

Education Requirements

A Bachelor’s degree in Computer Engineering or Electrical Engineering with 7+ years of relevant experience, or a Master’s degree with 5+ years of industry experience.