Senior IP Design Engineer

Role Summary

A Senior IP Design Engineer is sought for the development of high-speed connectivity IP portfolios associated with Lattice FPGAs. The role demands a strong technical lead who collaborates with architects to convert specifications into efficient RTL designs while optimizing for performance, power, and logic utilization.

Experience Level

Candidates should possess at least 7 years of experience specifically in FPGA IP design, showcasing a blend of technical skill and independent work ability.

Responsibilities

• Translate high-level specifications into high-speed RTL design.
• Ensure performance, power, and logic optimization in the designs.
• Conduct verification, debug, and timing closure on FPGA designs.
• Package soft IP and develop example designs and testbenches.
• Participate in hardware validation and interoperability tests.

Requirements

Key skills include experience with high-speed SERDES and video protocols such as DisplayPort, HDMI, and MIPI, as well as hands-on RTL design and programming skills (e.g., Verilog, SystemVerilog, C/C++, Perl, TCL, or Python). Knowledge in CDC/lint is also preferred.

Education Requirements

A minimum of a BS, MS, or PhD in Electronics or Computer Engineering is required to apply for this position.