Senior Full Chip Physical Design Engineer

Role Summary

The Senior Full Chip Physical Design Engineer will work on developing next-generation silicon for deployment in various infrastructures, contributing to the advancement of high-speed broadband connectivity. Candidates must possess design expertise and be able to collaborate effectively with cross-disciplines, including systems, firmware, and architecture teams.

Experience Level

This position for a Senior Full Chip Physical Design Engineer requires a minimum of 5 years of industry experience, particularly in ASIC design and physical design flows.

Responsibilities

• Execute SOC top level physical design tasks including floor-planning and timing analysis.
• Collaborate with various engineering teams to improve floorplanning and chip integration.
• Manage timing budgeting and constraints while ensuring closure and tapeout timelines are met.
• Conduct physical verification and compliance checks to avoid design rule violations.
• Adapt design flows to enhance overall design quality and integration requirements.

Requirements

Applicants must hold a Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science. Additionally, the ideal candidate should have a thorough understanding of SOC design flows and experience with industry EDA tools. Excellent problem-solving skills, a proactive work ethic, and strong scripting abilities are also essential.

Education Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science is mandatory.