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Senior FPGA Design Engineer

Advanced Micro Devices
Full-time
On-site
Santa Clara, California, United States
Level - Senior

Company Overview

Advanced Micro Devices (AMD) specializes in developing cutting-edge technology for the computing industry, focusing on various sectors such as AI, data centers, PCs, gaming, and embedded systems.

Role Summary

The Senior FPGA Design Engineer will work in the SBIO team to develop FPGA hardware validation platforms and debug complex issues. This position requires collaboration with design and firmware teams, ensuring successful execution of FPGA prototyping platforms from concept to production quality.

Experience Level

This role is classified as Level - Senior, aimed at candidates with extensive experience in FPGA design and hardware validation.

Responsibilities

  • Design, develop, and implement advanced FPGA architectures utilizing Xilinx devices.
  • Create RTL designs using Verilog/SystemVerilog for high-performance applications.
  • Engage in FPGA prototype design, implementation, and the subsequent bring-up activities.
  • Develop comprehensive design documentation and technical reports.
  • Conduct timing analysis and optimization using Vivado tools.
  • Perform board-level bring-up and system integration testing.
  • Utilize logic analyzers and oscilloscopes for debugging complex hardware/firmware issues.
  • Validate FPGA designs to meet specifications and performance requirements.
  • Independently resolve challenging technical issues.
  • Collaborate with hardware, software, and systems engineering teams.
  • Participate in design reviews and communicate project status to stakeholders.

Requirements

  • Strong analytical and problem-solving skills.
  • Excellent communication and leadership abilities.
  • Methodical with detailed attention in troubleshooting and problem-solving scenarios.
  • Possess a collaborative disposition for working with cross-functional teams.

Education Requirements

BS or higher degree in Electrical or Computer Engineering is desired.