Senior Engineer, Physical Design Engineering (ASIC)

Job Title

Senior Engineer, Physical Design Engineering (ASIC)

Role Summary

Senior Physical Design Engineer responsible for implementing complex digital and mixed-signal ASIC/SoC designs from floorplanning through tapeout. The role works across the backend flow to turn RTL and architecture into manufacturable silicon and collaborates with RTL, STA, DFT, verification, library and package teams.

Focus areas include placement, CTS, timing closure, physical verification, power and area optimization, and methodology improvements.

Experience Level

Senior-level. Preferred experience: typically 5+ years of relevant ASIC/SoC physical design experience, including successful implementation through tapeout.

Responsibilities

Lead and execute physical implementation tasks for assigned blocks or subsystems and drive signoff-ready deliverables.

• Own floorplanning, placement, clock tree synthesis, routing, and physical optimization for complex blocks or subsystems.
• Drive timing closure, congestion analysis, power reduction, and area optimization efforts.
• Perform and coordinate physical verification activities (DRC, LVS, ERC, reliability checks) with cross-functional teams.
• Develop and maintain constraints, scripts, and automated flows to improve quality and execution efficiency.
• Analyze and debug timing, signal integrity, power, and other backend implementation issues.
• Support block- and top-level integration: interface planning, timing alignment, and implementation readiness.
• Participate in design reviews and provide clear technical input on implementation trade-offs and risks.
• Mentor junior engineers and contribute to methodology and flow improvements.
• Support tapeout planning and execution to meet project milestones.

Requirements

Must-have technical skills, tools experience, and collaboration abilities required to perform the role.

• Proven track record in ASIC/SoC physical design and backend implementation through tapeout.
• Expertise in floorplanning, place-and-route, clock tree synthesis, timing closure and physical optimization.
• Strong understanding of timing analysis, constraints, signal integrity, and power optimization.
• Experience with industry-standard physical design and signoff tools (Cadence-based flows or equivalent).
• Scripting skills for automation and flow improvement (TCL, Python, or similar).
• Ability to collaborate effectively with RTL, STA, DFT, verification, library and package teams to resolve implementation issues.
• Strong problem-solving, debugging, and technical documentation skills; able to drive complex implementation workstreams independently.
• Nice-to-have: experience with advanced-node implementation, low-power methodologies, mixed-signal integration, and backend flow automation.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is preferred. Master's degree in a related field is also preferred. Equivalent combinations of education and experience (for example, education plus 5+ years of related experience) are acceptable.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.