Senior Engineer, Physical Design Engineering

Job Title

Senior Engineer, Physical Design Engineering

Role Summary

Responsible for the physical design (place-and-route) and sign-off of complex mixed-signal SoCs targeting advanced process nodes. The role works within the physical design engineering team to drive floorplanning, power planning, clock tree synthesis, parasitic extraction, static timing analysis, and tapeout activities to meet quality-of-results and schedule targets.

The position supports high-speed signal-processing hardware and multi-core systems-on-chip, collaborating with circuit, timing, and backend teams to deliver production tapeouts.

Experience Level

Senior-level. Posting specifies 4–8 years of relevant physical design/place-and-route experience.

Responsibilities

Primary responsibilities include hands-on physical implementation and tapeout leadership for high-speed SoCs:

• Implement and sign off PnR for complex high-speed SoC designs in advanced process technologies (e.g., 22 nm, 16 nm, 7 nm).
• Lead and execute tapeout activities and coordinate cross-functional tapeout readiness.
• Perform floorplanning, power planning, placement and routing, clock planning, and clock tree synthesis (CTS).
• Run parasitic extraction and oversee sign-off quality-of-results (QoR).
• Develop and validate timing constraints; perform static timing analysis and timing sign-off.
• Improve and automate flows to meet QoR targets and ensure predictability.
• Collaborate with circuit and process teams on device/interconnect considerations for UDSM technologies.
• Use scripting (TCL, Perl) to automate tasks and integrate tools.

Requirements

Must-have technical skills and experience:

• 4–8 years of hands-on experience in digital place-and-route and physical design for SoCs.
• Proven experience with PnR sign-off and handling tapeouts for complex, high-speed SoCs in advanced nodes.
• Strong expertise in static timing analysis, constraint development, and timing sign-off.
• Practical experience with floorplanning, power planning, placement & routing, clock planning/CTS, and parasitic extraction.
• Proficiency in scripting (TCL, Perl) for flow automation and tool integration.
• Willingness to travel approximately 10% of the time.

Nice-to-have:

• Understanding of device/interconnect and circuit aspects of ultra-deep-submicron (UDSM) technologies.

Education Requirements

BTech or MTech degree in Electrical/Electronic engineering (from a reputed institute) is specified in the posting.