Senior Engineer, Physical Design

Job Title

Senior Engineer, Physical Design

Role Summary

Implement physical design for UCIe PHY blocks and testchips from floorplanning through tapeout on advanced nodes (5nm and below). Work on synthesis, place-and-route, timing closure, and physical verification as part of an engineering team that interfaces with verification, DFT, IP integration, and foundry partners.

This role supports delivery of IP used in AI accelerators, data-center processors, and other high-performance systems.

Experience Level

Senior — posting lists 2–4 years of ASIC physical design experience; multiple advanced-node tapeouts and signoffs are expected.

Responsibilities

Primary responsibilities include owning physical implementation tasks and driving signoff across projects.

• Own physical implementation of UCIe PHY blocks and testchips from floorplanning to GDS.
• Drive synthesis, place-and-route, timing closure, and physical verification using DC, PT, ICC2/FC, and ICV.
• Collaborate with verification, DFT, and IP integration teams to resolve design issues and meet PPA targets without schedule slips.
• Lead design reviews, present tradeoff analyses, and make real-time floorplan and clock-tree decisions.
• Pilot and document new physical design flows and advanced-node methodologies for team adoption.
• Mentor junior engineers on timing closure, physical verification, and tool-chain best practices.
• Interface with foundry partners and customer engineering teams to resolve technology file, DRC/LVS, and silicon bring-up issues.

Requirements

Must-have technical skills and experience; listed "nice-to-have" items follow.

• Must-have: Hands-on ASIC physical design experience (posting lists 2–4 years) with ownership of SoC or IP tapeouts to GDS, including signoff responsibility.
• Must-have: Experience with advanced-node tapeouts (5nm or below) and practical FinFET physical design challenges (multi-patterning, EM, IR drop).
• Must-have: Proficiency with industry tools: Design Compiler (DC), PrimeTime (PT), ICC2/FC, and ICV.
• Must-have: Proven ability to drive timing closure, PPA tradeoffs, and meet schedule constraints across concurrent projects.
• Nice-to-have: Experience with DFT insertion, scan routing, ATPG, and debugging DFT-related timing/physical issues.
• Nice-to-have: Exposure to UCIe, SerDes, or other high-speed interface IP.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.