Senior Engineer in IO Layout Design

Role Overview

The Senior Engineer in IO Layout Design will focus on designing integrated circuit layout for a variety of applications. This role is critical to ensuring that the designs meet performance, power, and area specifications while adhering to strict design rules.

Position Summary

The selected candidate will be a part of a team that delivers high-quality electronic design automation solutions. You will work closely with other engineers to address design challenges and provide layout solutions that meet stringent deadlines.

Experience Level

This position requires a senior-level engineer with significant experience in integrated circuit layout design, particularly in IO design for various technologies.

Main Responsibilities

• Develop high-quality layouts for ASICs and FPGAs based on specifications and design rules.
• Conduct design rule checks (DRC) and layout versus schematic (LVS) verification.
• Work closely with circuit designers to optimize layouts for performance and manufacturability.
• Provide technical guidance and mentorship to junior engineers.
• Collaborate with cross-functional teams to ensure designs meet project requirements.

Required Qualifications

Applicants must have demonstrated expertise in IC layout design and proficiency with Cadence tools. Strong knowledge of semiconductor design processes and technologies is essential, along with excellent analytical and problem-solving skills.

Education Requirements

A degree in Electrical Engineering, Computer Engineering, or a related field, with advanced degrees preferred.