Senior Engineer — IC Design (Physical Design: PV/Power/EM/IR Drop)

Job Title

Senior Engineer — IC Design (Physical Design: PV/Power/EM/IR Drop)

Role Summary

Join the Silicon Engineering team in Hyderabad to lead physical verification and EM/IR drop analysis for advanced low-power SoCs. The role drives PV sign-off, static and dynamic IR analysis, floorplan and power-grid fixes, and cross-functional integration with PnR, floorplan, IO/packaging and foundry teams.

This is a hands-on engineering role with mentoring responsibilities and opportunities to improve EDA automation and verification methodology.

Experience Level

Senior-level. The posting specifies 4+ years of ASIC physical design experience.

Responsibilities

Primary responsibilities include ownership of physical verification and power/EM/IR analysis across SoC projects and mentoring junior engineers.

• Lead end-to-end low-power physical verification flow: DRC, LVS, PERC, resistance checks from RTL handoff to GDSII.
• Run static and dynamic IR analysis; define and execute signal and power EM strategies.
• Investigate grid weaknesses, perform RCA, and implement fixes to meet IR-drop targets.
• Collaborate with floorplan, PnR, IO ring, packaging, and PG teams for integration and alignment.
• Manage GDS streamout, version checks, PG fill insertion, and density/PG verification.
• Drive EDA tool automation and methodology improvements for scalability and efficiency.
• Work with foundries and vendors on process bring-up, PDK updates, and tape-out readiness.
• Mentor and act as domain single point of contact (SPOC) for junior engineers.

Requirements

Must-have skills and experience for immediate contribution.

• 4+ years of ASIC physical design experience with focus on PV, power, EM, and IR drop analysis.
• Hands-on experience with industry-standard tools (examples: Cadence Innovus, Voltus; Pegasus; Mentor/Calibre).
• Deep understanding of the architecture-to-GDSII flow and sign-off requirements.
• Proven ability to run static/dynamic IR analysis and provide actionable feedback.
• Strong problem-solving, leadership, and communication skills.

Nice-to-have:

• Experience in chip-level integration and hierarchical design methodologies.
• Familiarity with place-and-route workflows and static timing analysis (e.g., IRSTA).
• Knowledge of UPF/CPF, power gating, DVFS and other low-power techniques.
• Experience with cross-site collaboration and multi-team projects.

Education Requirements

Bachelor's or Master's degree in Electrical & Computer Engineering (ECE), Electrical & Electronics Engineering (EEE), or a related technical field (as listed in the posting).

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.