Role Summary
We are seeking an experienced Hardware Emulation Engineer to lead the deployment, optimization, and debug of large-scale SoC designs on hardware emulation platforms such as Synopsys ZeBu, Siemens Veloce, or Cadence Palladium. Collaboration with design, verification, software, and validation teams is essential to accelerate pre-silicon bring-up, software development, and system-level power and performance analysis.
Experience Level
4-8 years of experience in ASIC/SoC verification or emulation is required.
Responsibilities
Key responsibilities include:
- Leading emulation compilation, partitioning, mapping, and bring-up of sophisticated SoC and subsystem RTL designs.
- Developing and maintaining automated emulation flows and scripts (TCL, Python, Makefiles).
- Collaborating across RTL, verification, and software teams to integrate IP, debug issues, and enable pre-silicon software bring-up.
- Implementing and optimizing transactors, virtual bridges, and hybrid co-simulation for software execution.
- Working with EDA vendors to evaluate new emulator features and drive performance improvements.
- Mentoring junior engineers on flows and methodologies.
Requirements
Required qualifications include:
- A degree in Electronics, Computer Engineering, or equivalent.
- Hands-on experience with at least one major emulation platform from EDA vendors like Synopsys, Siemens, or Cadence.
- Strong RTL, synthesis, and timing knowledge (SystemVerilog/Verilog/VHDL).
- Proficiency in debug tools and waveform analysis (SimVision, Verdi, or DVE).
- Solid understanding of transactors and standard interfaces (AXI, PCIe, DDR, USB, Ethernet, etc.).
- Skilled in C/C++, scripting and automation (Python, Perl, or TCL).
- Familiarity with SystemVerilog testbenches, acceleration, and SoC boot flows.
- Experience with CPUs and SoC boot flows, and firmware loading.
- Excellent problem-solving and cross-team collaboration skills.
Education Requirements
A degree in Electronics, Computer Engineering, or equivalent is preferred.