Senior Director of IO Analog Design Engineering

Role Overview

The Senior Director of IO Analog Design Engineering is responsible for overseeing the Hard IP and Test Chip Development team within the Central Engineering Group at Intel. This role involves shaping strategies for future IO and chiplet interconnect technologies.

Experience Level

This position requires an experienced candidate with significant expertise in analog IP development and team leadership, ideally with a minimum of 12 years in the field.

Core Responsibilities

• Developing and refining a multi-generational roadmap for high-speed serial IO (HSIO) and die-to-die (D2D) interface IP development.
• Engaging with senior architects and executives to align IP landing zones and execution plans.
• Leading teams across architecture, logic, validation, and analog design, ensuring high quality and timely delivery.
• Managing resources and requirements across multiple teams and locations.
• Driving efficiencies in development using AI solutions.
• Fostering a collaborative team culture that addresses issues proactively.

Essential Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or related field with 12+ years of relevant experience.
• Proven experience in analog IP development from concept through launch.
• At least 10 years in leadership roles within silicon teams.
• Familiarity with high-speed IO technologies (e.g., PCIe/CXL, USB Type C) and die-to-die technologies (e.g., UCIe).

Education Requirements

A minimum of a Bachelor's degree in Electrical Engineering, Computer Science, or a related field, with extensive experience in the industry.