Senior Director of Design Verification (Photonic Fabric)

Job Title

Senior Director of Design Verification (Photonic Fabric)

Role Summary

Lead Marvell's Photonic Fabric design verification organization in San Diego, building the team, verification methodology, and infrastructure for next-generation optical interconnect SoCs and IP. This role combines hands-on technical leadership in SystemVerilog/UVM verification with hiring, process definition, and cross-functional coordination to enable first-pass tapeout success.

This is a founding local leadership position: you will recruit engineers, define team culture and verification strategy, and partner with design, architecture, software, and emulation groups.

Experience Level

Senior. Experience guidance provided: typically 15+ years with a Bachelor's, 10+ years with a Master's, or 8+ years with a PhD (as stated by the employer).

Responsibilities

Primary responsibilities include technical leadership of verification efforts, building the team and infrastructure, and ensuring high-quality deliveries for complex IP and SoC projects.

• Define and execute verification strategy and detailed verification plans for IP and full-chip SoC projects.
• Architect and review SystemVerilog/UVM testbenches, including stimulus generators, scoreboards, constrained-random sequences, and coverage models.
• Develop and optimize regression frameworks, coverage tooling, and automation to improve verification efficiency.
• Collaborate with design, architecture, software, emulation, and tapeout teams to meet milestones and ensure first-pass tapeout success.
• Drive continuous improvement of verification methodologies and processes across the organization.
• Hire, mentor, and grow a world-class verification team and establish team culture and practices.
• Conduct rigorous testbench reviews and coordinate debug activities including gate-level simulation and post-silicon validation.

Requirements

Must-have technical skills and experience required to perform the role.

• Proven experience leading and building verification teams for complex IP and SoC projects.
• Deep expertise in SystemVerilog and UVM methodology, including constrained-random verification and coverage-driven techniques.
• Track record of achieving functional and code coverage closure on complex SoC or IP tapeouts.
• Strong scripting skills in Python for verification automation, infrastructure, and tooling.
• Experience with industry simulators such as Xcelium, Questa, or VCS.
• Experience with object-oriented design and implementation; strong software engineering practices.
• Excellent communication and cross-functional collaboration skills.
• Experience mentoring and developing junior verification engineers.

Nice-to-have:

• Experience with AI development tools applied to verification infrastructure or automation.
• Familiarity with protocols such as AMBA (AXI/AHB/APB), PCIe, Ethernet, I2C, SPI, or UART.
• Experience with ARM/processor subsystem verification, memory controllers, NoC, or cache designs.
• Working knowledge of C/C++ for reference modeling or firmware-driven verification.
• Familiarity with gate-level simulation and post-silicon validation debug.

Education Requirements

Requires a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 15+ years of relevant experience; or a Master's degree with 10+ years of experience; or a PhD with 8+ years of experience. (Degree-and-years combinations specified by employer.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.