Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Design-for-Test (DFT) engineer responsible for DFT specification, architecture, and implementation across ASIC/SoC products. Work with product and design teams to ensure high test coverage, low power impact, and reduced test time.

The role provides methodology support, flow automation, ATPG pattern delivery, and pre/post-silicon verification and debug. The engineer will work independently and mentor junior team members.

Experience Level

Senior — 6 to 8 years of directly related ASIC/SoC DFT experience.

Responsibilities

Principal responsibilities include DFT implementation, verification, and methodology support across product lines.

• Define DFT specifications and architecture; implement DFT using industry-standard methodologies and tools.
• Develop and maintain DFT flow automation and methodology improvements.
• Support product lines to achieve high test coverage, low power impact, and low test time.
• Produce high-quality, verified ATPG patterns and perform DFT verification.
• Perform pre- and post-silicon verification, silicon bring-up support, and failure analysis/debug.
• Mentor and guide junior DFT engineers and collaborate with peer organizations.
• Willingness to travel up to 10% for work-related activities.

Requirements

Must-have technical skills and experience, plus preferred (nice-to-have) items.

• Must-have:
  • 6–8 years of ASIC/SoC DFT experience.
  • Expert knowledge of DFT architecture and planning.
  • Hands-on experience with Tessent DFT tools.
  • Strong knowledge of Scan, Test Compression, At-Speed Test, MBIST, LBIST.
  • Hands-on Scan insertion, Compression insertion, On-Chip Clock Control insertion, ATPG, and DFT verification.
  • Gate-level simulation experience with SDF.
  • Silicon test bring-up support and failure analysis/diagnosis experience.
  • Scripting skills (Perl, Python, Tcl).
  • Good teamwork and strong written and verbal communication skills.
• Nice-to-have / Preferred:
  • Experience with Cadence and Synopsys DFT tools.
  • Familiarity with IEEE 1149 / JTAG and Static Timing Analysis.
  • Experience with BIST, synthesis and DFT insertion.
  • Experience with Low-Power Scan methodologies and UPF.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.