Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Responsible for defining and implementing design-for-test (DFT) architecture and flows for SoC and block-level designs. Works with product/test engineering, physical design, CAD teams and operations to optimize test coverage, test cost, and production readiness.

Team: DFT / Test Engineering supporting SoC development, insertion flows, ATPG, and post-silicon bring-up.

Experience Level

Mid-level — 4–8 years of industry experience in the DFT domain.

Responsibilities

Primary responsibilities include DFT architecture definition, implementation, simulation, and post-silicon support across block and top levels.

• Define and optimize DFT architecture: scan partitioning, compression, at-speed, IR, low-power scan, MBIST, and JTAG boundary scan.
• Collaborate with product/test engineering to map DFT to SoC architecture and test requirements.
• Develop and upgrade SCAN and MBIST insertion flows and implement ATPG flows for relevant fault models.
• Create and debug timing constraints for SCAN/MBIST modes; resolve timing violations.
• Perform SCAN, MBIST, and boundary-scan pattern simulation and develop solutions to test analog macros.
• Support post-silicon bring-up on ATE, perform failure analysis, and drive test cost and yield improvements.
• Work closely with physical design teams throughout development and mentor new team members on flows and methodology.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 4–8 years of hands-on DFT industry experience, including taking products from architecture through scan implementation and simulation to production.
• Experience with post-silicon bring-up and failure analysis.
• Proficient scripting in Perl, Python, or Tcl and practical experience with HDLs.
• Strong interpersonal and communication skills for cross-functional collaboration.
• Ability and willingness to travel (~10%).

Preferred / nice-to-have:

• Experience with Tessent DFT tools (SCAN, MBIST, LBIST, OCC, EDT, SSN, Boundary Scan).
• Exposure to deep-submicron effects and low-power implementation using UPF/CPF.
• Experience with Cadence implementation tools (Genus, Tempus) or timing-closure/physical design experience.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.