Senior DFT ATPG Engineer

Role Summary

The Senior DFT ATPG Engineer position involves working on advanced Design-for-Test (DFT) technologies at NVIDIA, focusing on contributing to the development, verification, and post-silicon validation of sophisticated semiconductor chips. The engineer will be responsible for state-of-the-art DFT/Automatic Test Pattern Generation (ATPG) flows and will own projects from architecture and planning to pattern generation and verification.

Experience Level

This position requires a minimum of 5 years of hands-on experience in DFT and ATPG development, along with a solid understanding of ASIC design processes and various ATPG tools.

Responsibilities

• Take full ownership of ATPG processes, managing tasks from architectural design and planning to verification and post-silicon diagnosis.
• Develop and maintain automation flows to optimize production testing time.
• Collaborate across teams including chip design, backend, and production to enhance DFT methodologies.

Requirements

• 5+ years of experience in DFT/ATPG practices.
• Technical proficiency in DFT ASIC Design and familiarity with ATPG tools, particularly Mentor TestKompress.
• Strong programming skills in scripting languages, including TCL, PRL, Python, and Unix shell scripts.
• Proactive and self-motivated with a commitment to learning and contributing.
• Knowledge of DFT concepts such as scan, BIST, and fault simulation.

Education Requirements

A Bachelor’s degree in Electrical Engineering or Computer Engineering is required.