Senior Design Verification Engineer – SerDes IP

Role Summary

The role involves verifying complex SerDes digital and mixed-signal-adjacent subsystems in high-speed wireline transceivers at Advanced Micro Devices. The candidate will work closely with various teams to ensure correctness and high confidence across PVT, jitter/noise stress conditions, and protocol configurations using SystemVerilog and UVM.

Experience Level

This position requires a minimum of 5+ years of experience in design verification, particularly with a focus on SystemVerilog and UVM.

Key Responsibilities

The responsibilities include:

• Verification of SerDes digital IP blocks including DSP datapath, control loops, and ADC interfaces.
• Development of verification plans with clear coverage goals and realistic stimulus.
• Building and maintaining UVM environments with agents, drivers, monitors, and scoreboards.
• Collaboration with cross-functional teams to ensure alignment between RTL behavior and architectural intent.
• Mentoring junior engineers to enhance team verification quality.

Requirements

Candidates must have:

• Strong hands-on experience with SystemVerilog and UVM.
• A proven ability to build scoreboards, predictors, and reference models.
• Comfort in debugging complex issues using waveforms and logs.
• Programming skills in C/C++ or Python are a plus.

Education Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.

For further details regarding the application process, refer to the provided application URL.